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Multi-core processors contain multiple processing cores on a single chip, enabling parallel execution of tasks and improved overall system performance. This architecture has become the standard for modern computing from smartphones to supercomputers.
Power Wall: Clock speeds hit practical limits due to power consumption Memory Wall: Growing gap between processor and memory speeds Instruction-Level Parallelism (ILP) Wall: Diminishing returns from superscalar techniques Heat Dissipation: Higher frequencies generate excessive heat
Thread-Level Parallelism: Execute multiple threads simultaneously Better Resource Utilization: Cores can work on different tasks Power Efficiency: Lower clock speeds with more cores Scalability: Add cores instead of increasing frequency
Identical Cores: All cores have same architecture and capabilities Symmetric Processing: Any core can handle any task Examples: Intel Core series, AMD Ryzen Benefits: Simplified programming model, balanced performance
Different Core Types: Mix of high-performance and efficient cores Task Scheduling: OS assigns tasks based on performance requirements Examples: ARM big.LITTLE, Apple Silicon M-series Benefits: Better power efficiency, optimized for different workloads
big.LITTLE Architecture:
- Big Cores: High-performance, out-of-order execution
- LITTLE Cores: Power-efficient, in-order execution
- Migration: Tasks move between core types based on demand
- Cluster Switching: Switch between core clusters
Apple's Approach:
- Performance Cores: Maximum single-thread performance
- Efficiency Cores: Background tasks and light workloads
- Dynamic Scheduling: macOS scheduler optimizes core usage
- Unified Memory: Shared memory architecture
L1 Cache: Private to each core (instruction and data) L2 Cache: May be private or shared depending on design Benefits: No cache coherency issues for private data Drawbacks: No sharing of cached data between cores
L3 Cache: Typically shared among all cores Benefits: Efficient sharing of data between cores Challenges: Cache coherency protocols required Victim Cache: L3 may store data evicted from L2 caches
MESI Protocol (Modified, Exclusive, Shared, Invalid):
- Modified: Cache line modified, not in other caches
- Exclusive: Cache line present only in this cache
- Shared: Cache line present in multiple caches
- Invalid: Cache line not valid
MOESI Protocol: Adds "Owned" state for optimization Directory-Based: Scalable coherency for many cores Snooping: Cores monitor bus for coherency
Shared Bus: All cores share single bus Limitations: Bandwidth doesn't scale with core count Contention: Performance degrades with more cores Legacy: Used in early multi-core designs
Dedicated Links: Direct connections between components Scalability: Bandwidth scales with components Examples: Intel QPI/UPI, AMD Infinity Fabric Topology: Various topologies (mesh, ring, crossbar)
Packet-Based: Communication via packet switching Scalability: Supports many cores efficiently Routing: Adaptive routing for optimal paths Examples: Intel's mesh interconnect, ARM CoreLink
Threads: Multiple execution contexts in same address space Synchronization: Mutexes, semaphores, atomic operations APIs: Pthreads, Windows threads, C++11 threads Challenges: Race conditions, deadlocks, false sharing
Process-Based: Separate address spaces communicate via messages APIs: MPI (Message Passing Interface) Benefits: No shared state issues Overhead: Communication costs higher than shared memory
Tasks: Units of work that can execute in parallel Work Stealing: Idle cores steal work from busy cores Examples: Intel TBB, OpenMP tasks, Cilk Plus Benefits: Dynamic load balancing, easier programming
SIMD Operations: Same operation on multiple data elements Vector Instructions: SSE, AVX, NEON Auto-Vectorization: Compiler automatically parallelizes loops Examples: Array operations, image processing
Formula: Speedup = 1 / ((1-P) + P/N)
- P = Parallel portion of program
- N = Number of processors Implication: Serial portion limits maximum speedup Reality: Few programs are perfectly parallel
Concept: Problem size grows with available processors Formula: Speedup = N - α(N-1) Implication: Larger problems can achieve better parallel efficiency Real-world: More realistic for many applications
False Sharing: Cache line ping-ponging between cores Lock Contention: Multiple threads waiting for same resource Load Imbalance: Uneven work distribution among cores Memory Bandwidth: Shared memory bandwidth limitation
1:1 Model: One kernel thread per user thread N:1 Model: Many user threads to one kernel thread M:N Model: Many user threads to many kernel threads Hybrid: Combination of approaches
Mutexes: Mutual exclusion locks Condition Variables: Thread notification mechanism Semaphores: Counting synchronization primitive Atomic Operations: Hardware-supported atomic read-modify-write
Lock-Free Programming:
- Compare-and-Swap (CAS): Atomic update operation
- Memory Ordering: Control instruction and memory reordering
- ABA Problem: Value changes and changes back
- Hazard Pointers: Safe memory reclamation
Sequential Consistency: Operations appear in program order Relaxed Memory Models: Allow reordering for performance Memory Barriers: Enforce ordering constraints Examples: x86 (strong), ARM (weak), C++11 memory model
CPU Affinity: Bind threads to specific cores Load Balancing: Distribute work across cores NUMA Awareness: Consider memory topology Power Management: Balance performance and power
Completely Fair Scheduler (CFS): Linux default scheduler Windows Scheduler: Priority-based with aging Real-time Schedulers: Deterministic scheduling for RT systems User-space Schedulers: Application-controlled scheduling
Per-Core DVFS: Independent frequency control per core Turbo Boost: Temporarily exceed base frequency Power States: C-states for idle cores Thermal Throttling: Reduce frequency when overheating
Concept: Complete work quickly then enter low-power state Benefits: Better energy efficiency than running slowly Implementation: Boost frequency for short bursts Challenges: Workload characterization needed
Local Memory: Each processor has local memory Remote Memory: Access to other processors' memory Latency Differences: Local access faster than remote Bandwidth: Local memory has higher bandwidth
Memory Placement: Allocate memory close to using core Thread Placement: Schedule threads near their data First-Touch Policy: Memory allocated on first access Migration: Move pages to optimize access patterns
Definition: Processors with dozens to hundreds of cores Examples: Intel Xeon Phi, GPU compute units Applications: Highly parallel workloads Challenges: Programming complexity, memory bandwidth
Concept: Cores optimized for different tasks Examples: DSP + ARM cores, FPGA + processor Benefits: Specialized performance for specific workloads Complexity: Requires careful task partitioning
Specialized Cores: AI, cryptography, compression cores Domain-Specific: Cores optimized for specific applications Reconfigurable: FPGA-like adaptable cores Chiplet Designs: Mix and match different core types
Photonic Interconnects: Light-based communication 3D Integration: Vertical stacking of cores Wireless NoC: Wireless communication between cores Quantum Interconnects: Future quantum computing links
Parallel Languages: Languages designed for parallelism Automatic Parallelization: AI-assisted parallel code generation Distributed Computing: Seamless scaling beyond single chip Quantum-Classical Hybrid: Integration with quantum coprocessors